Recently, the memory card as a nonvolatile storage device mounting a flash memory of NAND type that is a nonvolatile memory as a programmable semiconductor device is expanding its market size as a storage medium for digital cameras and mobile telephones. Further, as an inexpensive storage device, aside from a memory card, for example, applications are expanding in HDD replacing SSD, memories to be mounted directly on host devices, etc.
At the same time, in the recent trend of downsizing of semiconductor device and process, the storage capacity has been increasing rapidly. The increase of storage capacity leads to increase of quantity of data to be stored in the storage medium. The increase of data capacity leads to demand for shortening of reading and writing time for the sake of convenience of access to the data.
On the other hand, downsizing of process has other effects, such as decline of reliability of flash memory. As the flash memory becomes smaller, the number of electrons for storing information decreases. It leads to various deterioration factors, such as retention, read disturb, and program disturb. It is hence generally proposed to enhance the reliability of the storage device using a flash memory by mounting an error correction function.
FIG. 9 is a block diagram of an example of nonvolatile storage device of a conventional storage device. Referring to FIG. 9, an application situation of error correction function is explained. A nonvolatile storage device 901 shown in FIG. 9 is composed of a controller 902 having an error correction function, and an nonvolatile memory 903. The nonvolatile storage device 901 is capable of writing or reading data from outside by specifying an address, and stores the written data without losing. The nonvolatile memory 903 is a memory for storing the data written in the nonvolatile storage device 901 within the nonvolatile storage device 901.
The controller 902 is composed of a host I/F (interface) 904, a buffer memory 905, and a memory I/F (interface) module 906. The buffer memory 905 is composed of a plurality of data buffers 907. The individual data buffers 907 can store data for the portion of one sector (512 bytes) each.
The memory I/F module 906 is composed of a memory I/F (interface) 909, an error code generation function part 910, a syndrome generation function part 911, an error position detection circuit 912, and an error correction circuit 913. The memory I/F module 906 transfers data between the corresponding nonvolatile memory 903 and buffer memory 905. The error code generation function part 910 generates an error correction code corresponding to the data to be written when writing data into the nonvolatile memory 903. The error correction code generated in the error code generation function part 910 is written into the corresponding nonvolatile memory 903 by way of the memory I/F 909.
The syndrome generation function part 911 reads out data and the corresponding error correction code and calculates the syndrome when the data is read out from the nonvolatile memory 903. The calculation result by the syndrome generation function part 911 is sent to the error position detection circuit 912. The error position detection circuit 912 calculates and determines the address position of the data having the error, on the basis of the syndrome sent from the syndrome generation function part 911. The error correction circuit 913 reads out the data of the address position determined by calculation in the error position detection circuit 912 from the data buffer 907, corrects the error, and writes back into the data buffer 907.
FIG. 10 is a block diagram of another example of nonvolatile storage device of a conventional storage device. The nonvolatile storage device shown in FIG. 10 has a plurality of nonvolatile memories connected to a plurality of I/Fs. The nonvolatile storage device shown in FIG. 10 controls the plurality of nonvolatile memories of the plurality of I/Fs. That is, since the plurality of I/Fs operate simultaneously, there are also a plurality of memory I/F modules, so that generation of error code and calculation of syndrome are executed in parallel.
As mentioned above, it is a generally known technique to enhance the reliability of flash memory by using such error correction function part. However, since the flash memory itself is lowered in reliability, an error correction circuit of higher performance and large error correction capacity is needed.
FIG. 11 is a table showing an example of circuit scale of error correction circuit in a conventional nonvolatile storage device. The numerical values shown in FIG. 11 show the ratio of error code generation function part, syndrome generation function part, and error correction function part in a circuit mounting a Read-Solomon code capable of correcting by 4 bytes per 528 bytes. As clear from the table in FIG. 11, the circuit scale of the error correction function part is larger than others.
The circuit scale of the error code generation function part and syndrome generation function part increases nearly in proportion to the number of bits of ECC code, but the error correction function part is an arithmetic unit, and if attempted to enhance the error correction capacity, the circuit scale increases rapidly.
The error code generation and the syndrome generation are executed simultaneously with data transfer to the nonvolatile memory. However, the error correction is processed independently after transfer, and its arithmetic processing speed has a direct effect on the entire processing speed of the storage device. From such viewpoint, too, the processing speed of error correction is demanded to be enhanced. However, increase of processing speed results in increase in circuit scale.
Patent document 1: Japanese Patent Application Laid-Open No. 10-145238